Blue Pearl Software Version 9.0 Creates a Debug Environment to Shorten Design Cycle Time

By CIOReview | Thursday, February 12, 2015
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SANTA CLARA, CA: Blue Pearl Software, the provider of EDA software that accelerates IP and FPGA verification, announces the release of version 9.0 of its software suite for Windows and Linux operating system.

This new software creates the new Blue Pearl Debug Environment that significantly reduces the time it takes designers to solidify RTL functionality.  This newly created environment enhances Blue Pearl’s Visual Verification Environment which includes additional time saving debug features of viewing schematic from messages, showing registers on clock paths, waivers capability, graphical representation of FSMs, CDC and false path viewers with cross probing to RTL, schematic representation of RTL with forward and reverse tracing, and linting message filtering.

 “The Blue Pearl Debug Environment changes the design exploration and debug game by providing functionalities that do not exist with other tools,” says Ellis Smith, Chairman and CEO, Blue Pearl Software. “With release 9.0 we are seeing up to 50percent runtime reduction in false path and multi cycle path generation for the largest customer designs.”

Key features of new software suite involves access to the HDL database once a design is loaded, RTL to schematic cross probe, advanced tracing to specific design elements, hierarchical name search and net coloring across hierarchy for ease of use.